The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for driving transistors. Merely by way of example, the invention has been applied for driving a transistor with a high threshold voltage. But it would be recognized that the invention has a much broader range of applicability.
In high voltage applications, a power field-effect transistor (FET) often should have a high drain-source breakdown voltage (e.g., >100 V). Such a power FET usually has a threshold voltage of 3-4 V. Using a gate driver with a low output voltage, for example, 5 V to drive the power FET often results in a high turn-on resistance or incomplete turn-on of the power FET. Hence, a gate driver with a relatively high output voltage that is larger than 5 V (e.g., the output voltage being 8-10 V) is often needed.
FIG. 1 is a simplified conventional diagram showing a system 100 for driving a transistor 104. The gate-driving system 100 includes a gate driver 102 and a transistor 104. The gate driver 102 includes a power source 122, and four inverters 124, 126, 128 and 130. The inverter 124 includes transistors 106 and 114 that are connected with each other, and the inverter 126 includes transistors 108 and 116 that are connected with each other. Additionally, the inverter 128 includes transistors 110 and 118 that are connected with each other, and the inverter 130 includes transistors 112 and 120 that are connected with each other. The four inverters 124, 126, 128 and 130 are connected in cascade. For example, the transistors 106, 108, 110, and 112 are P-channel FETs, and the transistors 114, 116, 118, and 120 are N-channel FETs. In another example, the transistor 104 is a power FET. The power source 122 provides a low-level bias voltage 132 (e.g., GND) and a high-level bias voltage 134 (e.g., VDD) to each of the cascaded inverters 124, 126, 128 and 130.
An input signal 136 (e.g., GATE_IN) is received by the cascaded inverters 124, 126, 128 and 130, and in response the gate driver 102 generates an output signal 138 to drive the transistor 104. Specifically, in operation, the inverter 124 receives the input signal 136 (e.g., GATE IN), and generates a first inverted signal 140. The inverter 126 receives the first inverted signal 140, and generates a second inverted signal 142 which is received by the inverter 128. The inverter 128 then generates a third inverted signal 144 which is received by the inverter 130. The inverter 130 finally generates the output signal 138 for driving the transistor 104. For example, if the input signal 136 is at a logic high level, the transistor 106 is turned off and the transistor 114 is turned on. Then the first inverted signal 140 is generated to be approximately equal to the low-level bias voltage 132 (e.g., GND). The inverter 126 receives the first inverted signal 140, and the transistor 108 is turned on while the transistor 116 is turned off The second inverted signal 142 is generated to be approximately equal to the high-level bias voltage 134 (e.g., VDD). In turn, the third inverted signal 144 is approximately equal to the low-level bias voltage 132 (e.g., GND), and the output signal 138 is approximately equal to the high-level bias voltage 134 (e.g., VDD). Then, the transistor 104 is turned on by the output signal 138 if the transistor 104 is an N-channel FET. In another example, when the input signal 136 is at a logic low level, then the transistor 104 is turned off by the output signal 138 if the transistor 104 is an N-channel FET.
Usually, the transistors in the gate driver 102 (e.g., the transistor 106, etc.) are high voltage devices of which manufacturing costs are often high. Further, these transistors usually have high turn-on resistance, and low driving capability per unit area. Hence, to drive a same load, the transistors in the gate driver 102 often use larger areas than low voltage devices.
To improve the driving capability per unit area, a bootstrap structure and low voltage devices are often used in a gate driver. FIG. 2 is a simplified conventional diagram showing a system 200 with a bootstrap structure for driving a transistor 204 . The gate-driving system 200 includes a gate driver 202 and a transistor 204. The gate driver 202 includes a low-side driver 206, a high-side driver 208, and a power source 210. The gate driver 202 further includes a bootstrap terminal 248 (e.g., BS). The low-side driver 206 includes the inverters 212, 214, 216 and 218, and a transistor 220. The high-side driver 208 includes the inverters 222, 224, 226 and 228, a level shifter 230, a transistor 232, a boost capacitor 234, and a diode 236. The inverters 212, 214, 216 and 218 are connected in cascade, and the inverters 222, 224, 226 and 228 are connected in cascade. For example, the transistors 220 and 232 are lateral-diffused MOSFETs (LDMOSs), such as lateral-diffused N-channel MOSFETs. In another example, the transistor 204 is a power FET.
The power source 210 provides a high-level bias voltage 238 (e.g., VDD) and a low-level bias voltage 246 (e.g., GND) to each of the inverters in the low-side driver 206. An input signal 240 (e.g., GATE_IN) is provided to both the low-side driver 206, and the high-side driver 208, and the gate driver 202 generates in response an output signal 242 to drive the transistor 204. Specifically, in operation, in the low-side driver 206, the inverter 212 receives the input signal 240 (e.g., GATE IN), and generates a first inverted signal 260. The inverter 214 receives the first inverted signal 260, and generates a second inverted signal 262 which is received by the inverter 216. The inverter 216 then generates a third inverted signal 264 which is received by the inverter 218. The inverter 218 generates a signal 244 to drive the transistor 220. If the transistor 220 is turned on by the signal 244 while the transistor 232 is off, then the output signal 242 (e.g., GATE_OUT) becomes approximately equal to the low-level bias voltage 246 (e.g., GND). For example, the high-level bias voltage 238 (e.g., VDD) is 5 V.
On the other hand, the input signal 240 is also received by the level shifter 230, and in response the level shifter 230 generates a signal 256. The cascaded inverters 222, 224, 226 and 228 receive the signal 256, and generate a signal 258 to drive the transistor 232. A high-level bias voltage 252 (e.g., VCC) is provided to the transistor 232. If the transistor 232 is turned on by the signal 258 while the transistor 220 is off, then the output signal 242 (e.g., GATE_OUT) becomes approximately equal to the high-level bias voltage 252 (e.g., VCC). For example, the bias voltage 252 (e.g., VCC) is 10 V.
The boost capacitor 234 operates to increase the voltage of the bootstrap terminal 248 (e.g., BS) to be larger in magnitude than the output signal 242 (e.g., GATE_OUT) by a predetermined voltage, and to provide a voltage 250 for the high-side driver 208 to operate. The diode 236 operates to rectify a current 254 flowing from the power source 210 to the diode 236 in order to prevent a current flowing from the high-side driver 208 to the power source 210 if the voltage of the bootstrap terminal 248 (e.g., BS) becomes larger than the bias voltage 238 (e.g., VDD) provided by the power source 210.
The conventional gate driver 202 usually uses a bootstrap structure including the boost capacitor 234 and the bootstrap terminal 248 (e.g., BS) to provide a proper operating voltage for the high-side driver 208. However, the boost capacitor 234 often has a capacitance of tens or hundreds of nanofarads, and hence may not be easily incorporated into an integrated-circuit (IC) chip. Further, the bootstrap terminal 248 is not suitable if terminals (e.g., pins) are limited on an IC chip. Additionally, the diode 236 is usually needed for the gate driver 202 for rectifying the current 254. If the diode 236 is a Schottky diode which often has good performance for rectification, manufacturing costs may increase.
Hence it is highly desirable to improve techniques of driving transistors with high threshold voltages.